1. Field of the Invention
The invention relates to a method of electrolytically forming conductor structures from highly pure copper, for example conductor paths, through-holes, connection contactings and connection places, on surfaces of semiconductor substrates (wafers), which surfaces are provided with recesses, when producing integrated circuits, more especially in cases where the recesses have a high aspect ratio.
2. Description of Related Art
To produce integrated circuits, the so-called silicon planar technique is used, wherein epitaxy and doping methods are employed. For such purpose, monocrystaline silicon discs, so-called wafers, are processed by physical methods in order to form variably conductive regions on the silicon surface in the micrometer range and, for some time, also in the sub-micrometer range (presently 0.25 xcexcm).
The production process can be divided into three steps:
(a) production of transistors and mutual oxidation thereof; this process is also called FEOL (Front End of Line) (xe2x80x9cTechnologie hochintegrierter Schaltungenxe2x80x9d, D. Widmann, H. Mader, H. Friedrich, 2nd Edition, Springer-Verlag, 1996; xe2x80x9cVLSI-Electronic Microstructure Sciencexe2x80x9d, Norman G. Einspruch, Editor, more esp. Vol. 19xe2x80x9cAdvanced CMOS Technologyxe2x80x9d, J. M. Pimbley, M. Ghezzo, H. G. Parks, D. M. Brown, Academic Press, New York, 1989);
(b) contacting and connection of the individual mono- and polycrystalline silicon regions of the FOEL part according to the desired integrated circuit;
(c) passivation or protection against mechanical damage or against the penetration of foreign substances.
In the second step, the transistors are generally contacted by multilayer metallisation and interconnected, the dielectric silicon dioxide being usually used for isolating the conductor tracks formed therefor.
To produce the conductor paths, the connection contacting holes and the connection places, an aluminium layer, having a thickness generally of 1 xcexcm, has been applied for a long time by physical methods, for example a vaporisation method (electron beam evaporation method) or a sputtering method. Said layer is subsequently structured by suitable etching methods using a photoresist.
Aluminium is described, in older literature, as the most advantageous alternative of the materials available for producing conductor paths, connection contactings and connection places. For example, demands on this layer are described in xe2x80x9cIntegrierte Bipolarschaltungenxe2x80x9d by H.-M. Rein and R. Ranfft, Springer-Verlag, Berlin, 1980. The problems mentioned there are in fact minimised by specific method optimisations, but they cannot be completely avoided.
More recently, it has been possible to replace aluminium by electrolytically deposited copper (IEEE-Spektrum, Jan. 1998, Linda Geppert, xe2x80x9cSolid Statexe2x80x9d, Pages 23 to 28). Because of the greater electrical conductance, the greater thermal resistance and the resistance to diffusion and migration, more especially, copper has proved to be an alternative to aluminium as the preferred material. For such purpose, the so-called xe2x80x9cDamascenexe2x80x9d technique is employed (IEEE-Spektrum, Jan. 1998, Linda Geppert, xe2x80x9cSolid Statexe2x80x9d, Pages 23 to 28, and P. C. Andricacos et al. in IBM J. Res. Developm., Vol. 42. Pages 567 to 574). For such purpose, a dielectric layer is initially applied to the semiconductor substrate. The required vias and trenches are etched to receive the desired conductor structures, usually by a dry-etching method. After a diffusion barrier (mainly titanium nitride, tantalum or tantalum nitride) and a conductive layer (mainly sputtered copper) have been applied, the recesses, i.e. the vias and trenches, are electrolytically filled by the so-called trench-filling process. Since, in such case, the copper is deposited over the entire surface, the excess at the undesired locations has to be subsequently removed again. This happens with the so-called CMP process (Chemico-mechanical polishing). Multilayer circuits can be produced by repeating the process, i.e. repeated application of the dielectric (for example of silicon dioxide) and formation of the recesses by etching.
The technical demands on the electrolytic copper deposition process are given hereinafter:
(a) Constant layer thickness over the entire wafer surface (planarity); the smaller the deviations from the intended layer thickness, the easier is the subsequent CMP process;
(b) Reliable trench-filling, even of very deep trenches, with a high aspect ratio; in the future, aspect ratios of 1:10 are expected;
(c) Greatest possible electrical conductance and, hence, automatically the greatest purity of the deposited copper; for example, it is necessary for the sum of all of the impurities in the copper layer to be less than 100 ppm (0.01% by wt.).
It has become apparent that this technique for producing the conductor paths, connection contactings and connection places presents advantages over the aluminium used hitherto. However, disadvantages have now also become apparent when using the plating method of prior art, and such disadvantages lead to a reduction in the yield or, at least, to high costs for the production:
(a) When soluble anodes are used, it is disadvantageous for the geometry of the anodes to change slowly during the deposition process, since the anodes dissolve during the deposition process, with the result that it is impossible to achieve any dimensional stability and, hence, also any constant field line distribution between the anodes and the wafers. In order to overcome this problem, at least partially, inert containers for chunky anode material are in fact used, so that the dimensions of the anodes do not vary too much during the deposition process, and dissolved anodes can be replaced again relatively easily. While these so-called anode baskets are being supplemented with fresh anode material, however, the deposition process has to be stopped, so that, when the process is started-up afresh, only test samples can initially be processed because of the resultant changes in the bath, in order to achieve constant stationary conditions of the process again. Moreover, each change of anode leads to a contamination of the bath because of impurities being separated from the anodes (anode slime). Also, in consequence, a longer start-up time is required after the topping-up of anodes.
(b) Moreover, copper which is dissolved in the bath weakens during the copper deposition. If copper salts are then supplemented in the bath, this leads to a variable content of copper in the solution. In turn, in order to keep such content constant, considerable outlay in respect of control engineering has to be involved.
(c) Furthermore, when insoluble anodes are used, there is a risk of gases being developed at the anodes. During the deposition process, these gases separate from the anodes, which are usually kept horizontal, and rise upwardly in the deposition solution. There, they encounter the wafers, which are also usually kept horizontal and are situated opposite the anode, and they precipitate on the lower surface of said wafers. The locations on the wafer surface, on which the gas bubbles settle, are screened from the homogeneous electrical field in the bath, so that no copper deposition can occur there. The regions which are disturbed in such manner may lead to the wafer or at least parts of the wafer being rejected.
(d) Moreover, insoluble anodes are destroyed when pulse techniques are used, because the noble metal coatings are dissolved.
(e) Furthermore, no phase boundaries are allowed to form in the copper-filled recesses because of a copper layer, which grows from the base of the recesses and/or the lateral faces, or even cavities in the copper. This has been described, for example, by P. C. Andricacos et al., ibid. An improvement was achieved there by adding additives to the deposition bath, which additives serve to improve the layer properties.
(f) An additional substantial disadvantage resides in the fact that the applied copper layer has to be very flat. Since the copper layer is formed both in the recesses and on the raised locations of the wafer, a copper layer is produced, which has a very non-uniform thickness. When the Damascene technique is used, the surface is smoothed by the CMP method. In such case, the increased polishing rate (dishing) over the structures (trenches and vias) can be disadvantageous. The best result in the publication by P. C. Andricacos et al., ibid is shown by a copper layer where there is another slight indentation over the recesses. This indentation also leads to problems during polishing.
In consequence, the basic object of the present invention is to avoid the disadvantages of known methods and, more especially, to minimise the increased contamination of the copper coatings obtained when the more advantageous insoluble anodes are used. Moreover, it is desirable to prevent electrolyte inclusions from forming in the copper structure when forming the copper structures in recesses having a large aspect ratio. Furthermore, the problems which result from supplementing the copper salts in the deposition solution are to be solved. It is also very important to overcome the dishing problem.
These problems are solved by the method according to the present invention.
The invention relates to a method of electrolytically forming conductor structures from highly pure copper on surfaces of semiconductor substrates (wafers), which surfaces are provided with recesses, when producing integrated circuits. The method according to the present invention includes the following method steps: a. coating the surfaces of the semiconductor substrates, which are provided with the recesses, with a full-surface basic metal layer in order to achieve sufficient conductance for the electrolytic deposition; b. full-surface deposition of copper layers, of uniform layer thickness, on the basic metal layer by an electrolytic metal deposition method by bringing the semiconductor substrates into contact with a copper deposition bath, the copper deposition bath containing at least one copper ion source, at least one additive compound for controlling the physico-mechanical properties of the copper layers as well as Fe(II) and/or Fe(III) compounds, and an electric voltage being applied between the semiconductor substrates and dimensionally stable counter-electrodes, which are insoluble in the bath and are brought into contact therewith, so that an electric current flows between the semiconductor substrates and the counter-electrodes; c. structuring the copper layer.